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we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 1 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module 7 - 50 v / 2.5a / 2.5 - 15 v output description the vdrm series of the mag i3c power module family provide a fully integrated dc - dc power supply including the buck switching regulator and inductor in a package. the wpmdu1251501 offers high efficiency and delivers up to 2. 5 a of output current. it operates from 7 v input voltage up to 50 v. it is designed for fast transient response. it is available in a standard industrial high power density bqfn - 41 ( 9 x 1 1 x 2 . 8 mm) package with good thermal performance. the v drm regulators have an on - board protection circuitry to guard against thermal overstress and electrical damage featuring t hermal shut down, over - current, short - circuit, overvoltage and under voltage protections. typical applications ? point - of - load dc - dc applications from 12v and 24v industrial rail s ? industrial, test & measurement, medical applications ? system power supplies ? dsps, fpgas, mcus and mpus supply ? i/o interface power supply features ? peak efficiency up to 96 % ? current capability up to 2. 5 a ? wide input voltage range: 7 v to 50 v ? 65v t ransients capability ? output voltage range: 2.5 v to 15 v ? continuous output power: 37.5 w ? integrated shielded inductor solution for quick time to market and ease of use ? adjustable switching frequency (0.3 to 1mhz) ? current mode control ? under voltage lockout p rotection (uvlo) ? adjustable soft - start and voltage tracking ? f requency synchronization with external clock ? thermal shut down and o utput short circuit protection ? cycle by cycle current limit ? power good ? operati ng ambient temp erature up to 85 c ? operating junction t emp . range: - 40 to 10 5c ? rohs & reach compliant ? mold compound ul 94 class v0 (flammability testing) certified ? complies with en 55022 class b radiated and conducted emissions standard typical circuit diagram c i n e n / u v l o v i n r t / c l k p g n d s s / t r k f b v o u t m o d u l e r s e t c o u t a g n d 2 6 2 7 3 1 2 8 3 6 v i n v o u t i n t s s 2 9 p g 3 5 b q f n - 4 1
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 2 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module package pin description symbol pin type pin description vin 26 power the supply input pin is a terminal for an unregulated input voltage source. it is required to place the input capacitor nearby the vin pin and pgnd. vout 10, 11, 12, 13, 14, 15, 39 power the o utput v oltage pins are connected to the internal inductor. c onnect external bypass capacitors between these pins and pgnd. pgnd 16, 17, 18, 19, 20, 40 power this is the return current path for the power stage of the device. connect these pins to the load and to the bypass capacitors associated with vin and vout. pad 40 should be connected to pcb ground planes using multiple vias for good thermal performance. agnd 4, 5, 32, 33, 34, 37 supply these pins are connected to the internal analog ground (agnd) of the device. this node should be treated as the zero volt ground reference for the analog control circuitry. pad 37 should be connected to pcb ground planes using multiple vias for good therma l performance. not all pins are connected together internally. all pins must be connected together externally with a copper plane . connect agnd to pgnd at a single point (at the ground terminal of the first output capacitor). see layout section for recomme ndations. rset int 1 a nalog an internal resistor of 10k? is connected internally between r set int and fb. this is the low side resistor of the feedback voltage divider. must be connected to agnd. fb 36 input connect a resistor from the last output capacitor terminal to fb to set the output voltage. pgnd 40 vout 39 sw 41 sw 38 agnd 37 vout 11 vout 10 nc 9 nc 8 sw 7 sw 6 agnd 5 agnd 4 rccomp 3 comp 2 rset int 1 18 pgnd 17 pgnd 16 pgnd 15 vout 14 vout 13 vout 12 vout 21 sw 22 sw 23 sw 24 sw 20 pgnd 19 pgnd 25 boot 26 vin 27 en / uvlo 28 ss / trk 29 intss fb 6 pg 35 agnd 34 agnd 33 agnd 32 rt / clk 31 intrrt 30 top view pgnd 40 vout 39 sw 41 sw 38 agnd 37 bottom view 36 fb 35 pg 34 agnd 33 agnd 32 agnd 31 rt / clk 30 intrrt pgnd 18 pgnd 17 pgnd 16 vout 15 vout 14 vout 13 vout 12 vout 11 vout 10 nc 9 nc 8 sw 7 sw 6 agnd 5 agnd 4 rccomp 3 comp 2 rset int 1 21 sw 22 sw 23 sw 24 sw 20 pgnd 19 pgnd 25 boot 26 vin 27 en / uvlo 28 ss / trk 29 intss
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 3 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module pins for optional use symbol pin type pin description en /uvlo 27 input enable and uvlo adjust pin. use an open drain or open collector logic device to ground this pin to disable the device . a resistor divider between this pin, agnd, and vin sets the uvlo voltage. rt/clk 31 input this pin sets the switching frequency. left open will set the internal oscillator to the default switching frequency . an external resistor from this pin to agnd sets a user defined switching frequency. this pin ca n also be used to synchronize with an external clock. intrrt 30 a nalog internal resistor (r rt int ) which defines the default switching frequency. must be connected to agnd. ss/trk 28 input soft - start and tracking pin. connecting an external capacitor to this pin adjusts the output voltage rise time during start - up . a voltage applied to this pin allows for tracking and sequencing control. intss 29 input internal soft - start or track feature select. connect this pin to agnd to enable the internal ss capacitor. leave this pin open to enable the tracking feature of pin ss/trk. pg 35 output power good flag pin. this open drain output asserts low if the output voltage is more than approximately 6% out of regulation. a pull - up resistor is required if this function is used. auxiliary pins description symbol pin type pin description comp 2 output output of the error amplifier. do not connect. this pin must be soldered to an isolated pad. rccomp 3 a nalog internal r and c of the compensation network. do not connect. this pin must be soldered to an isolated pad. boot 25 supply inte rnal bootstrap pin for the high - side mosfet . do not connect. this pin must be soldered to an isolated pad. sw 6, 7, 21, 22, 23, 24, 38, 41 power switch node. do not place any external component on these pins or tie them to a pin of another function. nc 8, 9 not connect . these pins are not connected to the internal circuitry, and are not connected to each other.
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 4 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module ordering information order code part description specifications package packing unit 171021501 wpmdu1251501nt 2.5a / 37.5w version bqfn - 41 tape and reel with 250 units 178021501 evaluation board 2.5a / 37.5w version 1 package specifications weight molding compound ul class certificate number 0.54g eme - g770h ul94 v - 0 e41429 sales information sales contacts wrth elektronik eisos gmbh & co. kg emc & inductive solutions max - eyth - str. 1 74638 waldenburg germany tel. +49 (0) 79 42 945 - 0 www.we - online.com powermodules@we - online.com
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 5 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module absolute maximum ratings caution: exceeding the listed absolute maximum ratings may affect the device negatively and may cause permanent damage. symbol parameter limits unit min max vin input voltage - 0.3 65 v vout output voltage - 0.6 v in v agnd agnd to pgnd - 0. 2 2 .3 v sw s witching node pin voltage - 0.6 65 v s witching node pin voltage ( 10ns transient ) - 2 65 v en /uvlo enable /u nder voltage lockout pin voltage - 0.3 5 v enable /u nder voltage lockout pin s ource current 100 a fb o utput voltage adjust pin voltage - 0.3 3 v pg power g ood pin voltage - 0.3 6 v power g ood pin s ink current 10 ma ss/trk soft - start/t racking pin voltage - 0.3 3 v soft - start/t racking pin s ink current 200 a intss internal s oft - s tart or tracking f eature select pin voltage - 0.3 3 v rt/clk timer/ clock pin voltage - 0.3 3.6 v timer/ clock pin s ource current 100 a t storage assembled, non operating storage temperature - 65 150 c t solr peak case/leads temperature during reflow soldering , max. 30sec per jedec j - std020 . maximum three cycles! 245 5c c mechanical shock mil - std - 883d, method 2002.3, 1msec, ? sine, mounted 1500 g mechanical vibration mil - std - 883d, method 2007.2, 20 - 2000hz 20 g operating conditions operating conditions are conditions under which operation of the device is intended to be functional. all values are referenc ed to gnd. symbol parameter min ( 1 ) typ ( 2 ) max ( 1 ) unit v in input v oltage 7 - 50 v v out regulated output voltage 2.5 15 v f sw switching frequency 300 - 1000 khz t a ambient temperature range - 40 - 85 (3) c t j junction t emperature range - 40 - 105 c i out nominal output current 2.5 a thermal specifications symbol parameter typ unit ja thermal resistance junction to a mbient ( 4 ) 14 c/w jt thermal resistance junction to top ( 5 ) 3.3 c/w jb thermal resistance junction to board ( 6 ) 6.8 c/w t sd thermal shut down, junction temperature, rising 180 c thermal shut down hysteresis, falling 15 c
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 6 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module electrical specifications min and max l imits are valid for the recommended ambient temperature range of - 40c to 8 5c . typical values represent statistically the utmost probability at following conditions: v in = 24 v, v out = 5.0 v, i out = 2.5 a, rt = open, c in = 2 x 2.2 f ceramic, c out = 2 x 47 f ceramic , unless otherwise specified. symbol parameter test conditions min ( 1 ) typ ( 2 ) max ( 1 ) unit output current i ocp over current protection - 5.1 - a accuracy v fb reference accuracy t a = 25c; i out = 100ma with internal feedback resistor - - 2.0 (7 ) % temperature variation - 40c t +85c - 0.5 1.0 % v out line regulation over input voltage range - 0.1 - % load regulation over output current range - 0.4 - % total output voltage variation includes set - point, line, load, and temperature variation - - 3.0 (7 ) % output voltage ripple 0.25a i 2.5a, v 3.3v - 1 - % of v out switching frequency f sw free - running oscillator frequency rt/clk pin open 300 400 500 khz f clk synchronization clock frequency range 300 - 1000 khz d clk synchronization clock duty cycle range 25 50 75 % v clk - h high - level threshold clk relative to agnd - 1.9 2.2 v v clk - l low - level threshold clk relative to agnd 0.5 0.7 - v enable and under voltage lockout v uvlo v in under voltage lockout no hysteresis, rising and falling - 2.5 - v v en en threshold trip point v en rising and falling, no hysteresis 1.15 1.25 1.36 (8 ) v i en en input current v en < 1.15v - - 0.9 - a v en > 1.36 v - - 3.8 - a i en to agnd, v en = 0v - 1.3 4 a power good pg power good thresholds v out rising, v out good - 94 - % v out rising, v out fault - 109 - % v out falling, v out good - 91 - % v out rising, v out fault - 106 - % power good low voltage i(pg) = 3.5ma - 0.2 - v efficiency efficiency v in = 24v, i out = 1.5 a, v out = 5 v, f sw = 500 khz - 84 - % v in = 48v i out = 1.5a, v out = 5v, f sw = 500 khz - 79 - %
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 7 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module symbol parameter test conditions min ( 1 ) typ ( 2 ) max ( 1 ) unit transient response t tr transient response recovery time 1a/s load step from 50 to 100%, - 400 - s v tr transient response v out over/undershoot 1a/s load step from 50 to 100%, - 90 - mv quiescent current i q input quiescent c urrent en = 0v, t a = 25c, 3.5v v in 60v 1.3 4 a non switching: v fb = 0.83v, t a = 25c, v in = 12 v 200 a reliability symbol parameter test conditions min ( 1 ) typ ( 2 ) max ( 1 ) unit mtbf mean time between failure s confidence level 60%, t a =55c, activation energy 0.7ev, 1000 hrs test duration, 4 6185 samples, 1 fail 1.79 10 9 h notes (1) min and max limits are 100% production tested at 25c. limits over the operating temperature range are guaranteed through correlation using statistical quality control (sqc) methods. (2) typical numbers are valid at 25c ambient temperature and represent statistically the utmost probability assuming the gaussian distribution. (3) depending on heat sink design, number of pcb layers, copper thickness and air flow. (4) m easured on a 100 x 100mm four layer board, with 35m (1 ounce ) copper , no air flow (5) the junction - to - top characterization parameter, jt , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51 - 2a (sections 6 and 7). t j = jt * pdis + t t ; where pdis is the power dissipated in the device and t t is the temperature of the top of the device. (6) the junction - to - board characterization parameter, jb , estimates the junction temperature, t j , of a device in a real system, using a procedure described in jesd51 - 2a (sections 6 and 7). t j = jb * pdis + t b ; where pdis is the power dissipated in the device and t b is the temperature of the board 1mm from the device. (7) the stated limit of the feedback voltage tolerance includes the tolerance of both the inter nal voltage reference and the internal adjustment resistor r set int . the overall output voltage tolerance is affected by the tolerance of the external r set resistor. (8) value when no volt age divider is present at the en /uvlo pin.
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 8 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module typical performance curve s if not otherwise specified, the following conditions apply: v in = 7 - 50 v; c in = 2x 2.2f x7r c eramic; c o = 2x 47 f x7r c eramic, t amb = 25c . 11 d ambient temperature [ c ] thermal derating : v in = 12 v ; v out = all voltages 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 output current [ a ] natural convection 20 30 40 50 60 70 80 90 12 d ambient temperature [ c ] thermal derating : v in = 24 v ; v out = all voltages 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 output current [ a ] natural convection 20 30 40 50 60 70 80 90 1 5 d a m b i e n t t e m p e r a t u r e [ c ] t h e r m a l d e r a t i n g : v i n = 3 6 v ; v o u t = a l l v o l t a g e s 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 o u t p u t c u r r e n t [ a ] n a t u r a l c o n v e c t i o n 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 6 d a m b i e n t t e m p e r a t u r e [ c ] t h e r m a l d e r a t i n g : v i n = 4 8 v ; v o u t = a l l v o l t a g e s 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 o u t p u t c u r r e n t [ a ] n a t u r a l c o n v e c t i o n 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 9 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module typical performance curve s if not otherwise specified, the following conditions apply: v in = 7 - 50 v; c in = 2x 2.2f x7r c eramic; c o = 2x 47 f x7r c eramic, t amb = 25c . 0 10 20 30 40 50 60 70 30 100 1000 frequency [ mhz ] radiated emissions [ dbv / m ] radiated emissions 171021501 measured on evaluation board without input filter v in = 24 v , v out = 5 v , f sw = 500 khz , i load = 2 a horizontal vertical en 55022 class a limit en 55022 class b limit 0 10 20 30 40 50 60 70 30 100 1000 frequency [ mhz ] radiated emissions [ dbv / m ] radiated emissions 171021501 measured on evaluation board with input filter c f = 2 . 2 f and l f = 22 h v in = 24 v , v out = 5 v , f sw = 500 khz , i load = 2 a horizontal vertical en 55022 class a limit en 55022 class b limit 0 10 20 30 40 50 60 70 0 . 15 1 10 frequency [ mhz ] conducted emissions [ dbv / m ] conducted emissions 171021501 measured on evaluation board with input filter c f = 2 . 2 f and l f = 22 h v in = 24 v , v out = 5 v , f sw = 500 khz , i load = 2 a average quasi peak en 55022 class b quasi peak limit en 55022 class b average limit 80 - 10 30 0 . 5
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 10 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module typical performance curve s if not otherwise specified, the following conditions apply: v in = 7 - 50 v; c in = 2x 2.2f x7r c eramic; c o = 2x 47 f x7r c eramic, t amb = 25c . 0 1 d e f f i c i e n c y [ % ] o u t p u t c u r r e n t [ a ] e f f i c i e n c y : v i n = 1 2 v @ t a m b = 2 5 c 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 1 0 0 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 0 5 d p o w e r l o s s [ w ] o u t p u t c u r r e n t [ a ] p o w e r l o s s : v i n = 1 2 v @ t a m b = 2 5 c v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 0 1 2 3 4 5 6 0 2 d e f f i c i e n c y [ % ] o u t p u t c u r r e n t [ a ] e f f i c i e n c y : v i n = 2 4 v @ t a m b = 2 5 c 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 1 0 0 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z 0 6 d p o w e r l o s s [ w ] o u t p u t c u r r e n t [ a ] p o w e r l o s s : v i n = 2 4 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 0 1 2 3 4 5 6 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z 0 3 d e f f i c i e n c y [ % ] o u t p u t c u r r e n t [ a ] e f f i c i e n c y : v i n = 3 6 v @ t a m b = 2 5 c 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 1 0 0 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z 0 7 d p o w e r l o s s [ w ] o u t p u t c u r r e n t [ a ] p o w e r l o s s : v i n = 3 6 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 0 1 2 3 4 5 6 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 11 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module typical performance curve s if not otherwise specified, the following conditions apply: v in = 7 - 50 v; c in = 2x 2.2f x7r c eramic; c o = 2x 47 f x7r c eramic, t amb = 25c . 0 4 d e f f i c i e n c y [ % ] e f f i c i e n c y : v i n = 4 8 v @ t a m b = 2 5 c v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z 5 0 5 5 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 1 0 0 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 o u t p u t c u r r e n t [ a ] 0 8 d p o w e r l o s s [ w ] o u t p u t c u r r e n t [ a ] p o w e r l o s s : v i n = 4 8 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 0 1 2 3 4 5 6 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z 0 9 d o u t p u t v o l t a g e r i p p l e [ m v ] o u t p u t v o l t a g e r i p p l e : v i n = 1 2 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 o u t p u t c u r r e n t [ a ] 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z 1 0 d o u t p u t v o l t a g e r i p p l e [ m v ] o u t p u t v o l t a g e r i p p l e : v i n = 2 4 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 o u t p u t c u r r e n t [ a ] 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z 1 3 d o u t p u t v o l t a g e r i p p l e [ m v ] o u t p u t v o l t a g e r i p p l e : v i n = 3 6 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 o u t p u t c u r r e n t [ a ] 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z 1 4 d o u t p u t v o l t a g e r i p p l e [ m v ] o u t p u t v o l t a g e r i p p l e : v i n = 4 8 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 o u t p u t c u r r e n t [ a ] 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 12 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module block diagram c ircuit description the magi3c power module wpmdu1251501 is based on a non synchronous step down regulator with integrated mosfet , s c hottky diode and a power inductor. the control scheme is based on a current mode (c m ) regulation loop. the v out of the regulator is divided with the feedback resistor network r set and an internal 10k ? resistor and fed into the error amplifier which compares this signal with the internal 0. 8 v reference v ref . the error signal is amplified and controls the on - time of a fixed frequency pulse with generator. this signal drives the power mosfet . the current mode architecture features a constant frequency during load steps. only the on - time is modulated. it is internally compensated and stable with low esr output capacitors and requires no external compensation network. t his architecture supports fast transient response and very small output ripple values (less than 10mv) are achieved. intss rt / clk pg fb ss / tr sw en / uvlo vout pgnd pwm controller driver protection circuitry boo t rccomp intr rt agnd comp 29 2 3 1 27 35 c out r set v out agnd pgnd linear regulator vin uvlo c in v in pgnd rset int 36 c boot 25 4 . 9 h vin 26 2 a v r ef agnd pgnd 28 31 30 10 - 15 , 39 6 , 7 , 21 - 24 , 38 , 41 0 . 8 v power module error amplifier 10 k
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 13 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module design flow the next 10 simple steps will show how to select the external components to design your power a pplication . essential steps 1. set output voltage 2. set operating frequency 3. select input capacitor 4. select output capacitor optional steps 5. select soft - start capacitor 6. select under voltage lockout divider 7. enable/disable 8. voltage tracking 9. synchronization to an external clock 10. power good step 1 s etting the output voltage (v out ) the magi3c power module is designed to provide output voltages from 2.5 v to 15 v. the output voltage is determined by the value of r set , which must be connected between the v out node and the fb pin (pin 36). for output voltages higher than 5 v, improved operating performance can be obtained by increas ing the operating frequency. this adjustment requires the addition of r rt between rt/clk (pin 31) and agnd (pin 30). see the step 2 set operating frequency section for more details. table 1 gives the standard external r set resistor for a number of common bus voltages and also includes the recommended r rt resistor for output voltages above 5 v. v out r set 2.5v 21.5 k? 3.3v 31.6 k? 5v 52.3 k? 9v 102k? 12v 140 k? 15v 178 k? c i n e n / u v l o v i n r t / c l k p g n d s s / t r k f b v o u t m o d u l e r s e t c s s c o u t a g n d 2 6 2 7 3 1 2 8 3 6 v i n v o u t i n t s s 2 9 p g 3 5 r u v l o 1 r u v l o 2 r r t 1 0 . 1 . 8 . 3 . 4 . 6 . 5 . 2 . 7 . 9 .
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 14 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module for other output voltages the value of r set can be calculated using the following formula. r set = 10 ? ( v out 0 . 798 ? 1 ) k ( 1 ) out put voltage range condition i nput voltage v out v in 50v in min out + 3v v in max out *15 v out > 12v v in min v out *1.33 v in max v out *15 although the device can safely handle input surge voltages up to 65 v, sustained operation at input voltages above 50 v is not recommended. see the step 6 ( undervoltage lockout (uvlo) threshold section ) for more information. step 2 setting the operating frequency (f sw ) nominal switching frequency of the magi3c power module is set from the factory at 400 khz. this switching frequency is optimized for output voltages below 5 v. for output voltages of 5 v and above, better oper ating performance can be obtained by raising the operating frequency. this is easily done by adding a resistor, r rt from the rt/clk pin (pin 31) to the agnd pin (pin 30). raising the operating frequency reduces output voltage ripple, lowers the load curren t threshold where pulse skipping begins, and improves transient response. the recommended switching frequency for typical output voltages is listed in table 2 . for the maximum recommended output voltage value of 15 v, the switching frequency computes to 1 mhz. operation above 1 mhz is not recommended. v out f sw r rt 2.5v 400khz open 3.3v 400khz open 5v 500khz 1,1m? 700khz 365k? 800khz 267k? 1mhz 178k? v out 36 r set 10 k agnd r set in t 1 fb
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 15 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module it is also possible to synchronize the switching frequency to an external clock signal. see the step 8.synchronization clk option section for further details. while it is possible to set the operating frequency higher than 400 khz when using the device at output voltages of 5 v or less, minimum duty cycle and pulse skipping issues restrict the maximum recommended input voltage under these conditions. the recommended operating conditions for the magi3c power module can be summarized by figure 1. the graph sh ows the maxi mum input voltage vs. output voltage restriction for several operating frequencies. the lower boundary of the graph shows the minimum input voltage as a function of the output voltage. figure 1 . input voltage vs . output voltage operating area 2 6 d 2 . 5 5 1 0 1 2 . 5 7 . 5 1 5 i n p u t v o l t a g e [ v ] o u t p u t v o l t a g e [ v ] f s w = 4 0 0 k h z f s w = 6 0 0 k h z f s w = 8 0 0 k h z f s w = 1 m h z v i n ( m i n ) r e c o m m e n d e d o p e r a t i n g a r e a 0 1 0 2 0 3 0 4 0 5 0 6 0
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 16 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module step 3 select input capacitor (c in ) the wpmdu1251501 magi3c power module contains no internal input capacitors. therefore an external input capacitance placed directly at the v in pin is required to handle the input ripple current of the application. the input capacitor can be several capacitors in parallel. input capacitor selection is generally directed to satisfy the input ripple current requireme nts rather than by capacitance value . input ripple current rating is dictated by the equation: i c inrms 1 2 ? i out ? d 1 ? d ( 2 ) where d v out v in (as a point of reference, the worst case ripple current will occur when the module is presented with full load current and when v in = 2 * v out ). if the system design requires a certain minimum value of peak - to - peak input ripple voltage ( v in ) be maintained then the following equation may be used. c in i out ? d ? ( 1 C d ) f sw ? v in ( 3 ) if v in is 1% of v in for a 24 v input to 5 v o utput application this equals 24 0 mv and f sw = 500khz. c in 2 . 5a ? 5v 24v ? ( 1 C 5v 24v ) 500000 ? 0 . 24v c in 3 . 4f recommende d minimum input capacitance is 4.4f x7r ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. it is also recommended that attention be paid to the voltage and temperature deratings of the capacitor selected. it should be noted that rip ple current rating of ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating. additional bulk capacitance with higher esr may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines.
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 17 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module step 4 select output capacitor (c out ) none of the required output capacitors is integrated within the module. . at a minimum, the output capacitor must meet the worst case rms current rating of 0 . 5 ? ? ? ? , as calculated in equation (4). ? i l = v out ? ( v in ? v out ) f sw ? l ? v in ( 4 ) beyond that, additional capacitance will reduce output ripple as long as the esr is low enough to permit it. there is no limit of the maximum output capacitance. please consider the derating of the nominal capacitance value due to temperature, aging and applied dc volt age (only for mlcc, e.g. x7r up to - 50%) . selection by output voltage ripple requirements the capacitor should be selected in order to minimize the output voltage ripple and provide a stable voltage at the output. under steady state conditions, the voltage rippl e observed at the output can be defined as: v out ripple = ? i l ? esr + ? i l ? 1 8 ? f sw ? c out ( 5 ) very low esr capacitors, like ceramic and polymer electrolytic, are re commended. if a low esr capacitor is selected, the equation (4) can be simplified and a first condition for the minimum capacitance value can be derived: c out ? i l 8 ? v out ripple ? f sw ( 6 ) l c out rload v in v out i l i out hs mosfet esr v es r v cout ls mosfet c in
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 18 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module the use of very low esr capacitors leads to an output voltage ripple as shown below: when capacitors with slightly higher esr are utilized, the dominant parameter which influences the output voltage ripple is just the esr: esr v out ripple ? i l ( 7 ) consequently the shape of the output voltage ripple changes, as shown below: -10 -5 0 5 10 0 1 2 3 output voltage ripple [mv] time [s] output voltage ripple with low esr capacitors -100 -50 0 50 100 0 1 2 3 output voltage ripple [mv] time [s] output voltage ripple with high esr capacitors
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 19 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module selection by load step requirements the output voltage is also affected by load transient (see picture below). by the output current transition from a low to a high value, the voltage at the output capacitor (v out ) drops. this involves two contributions. one is caused by the voltage drop across the esr (v esr ) and depends on the slope of the rising edge of the current step (t rise ) . for low esr values and small load currents, this is often negligible . it can be calculated as follows: v esr = esr ? ? i out ( 8 ) where ? ? ??? is the load step , as shown in the picture below (simplified: no voltage ripple is shown). the second component is the voltage drop due to discharge of the output capacitor, which can be estimated as: v discharge = ? i out ? t d 2 ? c out ( 9 ) i n a current mode architecture the t d is strictly related to the bandwidth of the regulation loop and influenced by the c out (increasing c out , the t d increases as well). 0 t i out 0 t v out ?i out ?v out v esr v discharge t d t reg t rise
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 20 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module in order to choose the value of the output capacitor, the following steps should be followed: 1. according to the operating conditions (v in , v out and f sw ), select the minimum c out recommended in table on page 3 8 . 2. measure t d . 3. calculate the appropriat e value of c out for the maximum voltage drop v discharge allowed at a defined load step, using the following equation (10), derived from equation (9): c out ? i out ? t d 2 ? v discharge ( 10 ) 4. as above mentioned, changing c out affects also t d . therefore a new measure should be performed and, if necessary, the step 2 and 3 should be repeated (it is an iterative process and few steps could be required). example . v in = 12 v, v out = 3.3 v, i out = 2a (from 0.5a to 2.5a) , f sw = 400k hz, v out <0.1v. acc ording to the table on page 3 8 , two output mlcc of 47f would be necessary. after mounting the s e capacitor s , the load transient should be performed and the t d measured (see picture below) . the v out = 0.13 v and t d = 3 s. it is important to remind that the v out includes also the voltage drop during t rise , mainly due to the esr (v esr = 6 0mv, see picture above) . in order to achieve the desired maximum v out , the v discharge should be below 0.025 v. using the equation (9), the minimum required output capacitor is: c out 2a ? 3 s 2 ? 0 . 025v = 120f to achieve the calculate d value of c out , an additional mlcc of 47f is mounted in parallel. - 0,3 - 0,2 - 0,1 0 0,1 0,2 0,3 -4 -3 -2 -1 0 1 2 3 4 0 10 20 30 40 50 60 v out (ac coupled) [v] i out [a] time [s] load transient with c out = 47f mlcc v out = 0.29v 6s v discharge = 0.2v v out i out
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 21 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module the result with three mlcc of 47f in parallel is shown below: in order to have a safer margin from the desired v out < 0.1v , additional capacitance at output would be required. - 0,30 - 0,20 - 0,10 0,00 0,10 0,20 0,30 -4 -3 -2 -1 0 1 2 3 4 0 20 40 60 80 100 120 v out (ac coupled) [v] i out [a] time [s] load transient with c out = 2x47f mlcc + 220f electrolytic v out i out v out = 0.16v 24s v discharge = 0.1v
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 22 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module step 5 select soft - start capacitor ( c ss ) programmable soft - start permits the regulator to slowly ramp up to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise - time to prevent overshoot. figure 2 . basic soft - start configuration in mini mum external components configuration (figure 2) , c onnecting the intss pin (pin 29) to agnd while leaving ss pin (pin 28) the magi3c power module power s - up with a soft - start interval of approximately 5ms , using the internal soft - start circuitry . this reduces the slope of the output voltage . the soft - start circuitry introduces a short time delay when a valid input voltage is recognized . figure 3 sh ows the start - up waveforms of the magi3c power module, operating from a 24 v input and the output voltage adjusted to 5 v. figure 3. startup v in =10v; i out =2a c i n e n / u v l o v i n r t / c l k p g n d s s / t r k f b v o u t m o d u l e r s e t c o u t a g n d 2 6 2 7 3 1 2 8 3 6 v i n v o u t i n t s s 2 9 p g 3 5 2 3 d v o u t v i n v p g 2 m s / d i v 1 0 v / d i v 2 v / d i v 5 v / d i v
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 23 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module for output voltages of 5 v or less, the soft - start capacitance built into the magi3c power module is sufficient for a turn - on ramp rate that does not induce large surge currents while charging the output capacitors. for output voltages higher than 5 v, an additional soft - start capacitance is recommen ded. for 12 v to 15 v output voltages, a 22 nf capacitor should be connected between the ss/trk pin (pin 28) and agnd, while connecting the intss pin (pin 29) to agnd as well . figure 4 shows an external ss capacitor connected to the ss pin and the intss pin connected to agnd. see table 3 below for ss capacitor values and timing interval. figure 4 . soft - start capacitor css and intss connection soft - start time t ss capacitor c ss 5ms open 7ms 4.7nf 10ms 10nf 13ms 15nf 17ms 22nf table 3 : recommended soft - start capacitors for typical start times s s / t r k a g n d i n t s s c s s o p t 2 8 2 9
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 24 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module step 6 optional: program under voltage lockout divider (r uvlo1 and r uvlo2 ) the function of the r uvlo1 and r uvlo2 divider is to allow the designer to choose an input voltage below which the circuit will be disabled. this implements the feature of programmable external undervoltage lockout. this is often used in battery powered sys tems to prevent deep discharge of the system battery. it is also useful in system designs for sequencing of output rails or to prevent early turn - on of the supply as the main input voltage rail rises at power - up . most systems will benefit by using the prec ision enable threshold to establish a system under voltage lockout. the recommended approach is to choose an input uvlo level higher than the target regulated output voltage for the stage. figure 5. en/uvlo configuration without resistive divider without an enable divider (figure 5) , this magi3c power module will attempt to turn on around 2.5 v ( v uvlo voltage threshold referenced to v in pin26). this would not be useful for a stage that ultimately might be creating 5vout. operation of the module on input voltage conditions below the nominal output should be avoided. systems that don't implement the enable divider will turn in early during the rise of vin and might not have monotonic rise in output voltage. many systems need smooth rise in supply voltage. i n the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power - up cycle than the magi3c power module output rail. figure 6. under voltage lockout (uvlo) schematic using the external e nable divider r uvlo1 and r uvlo2 as shown in figure 6 , the designer is able to precisely select the turn - on and turn - off thresholds of this magi3c power module . at turn - on, the v on uvlo threshold determines the input voltage level where the device begins power conversion. during the power - down sequence, the v off uvlo threshold determines the input voltage where power conversion ceases. e n / u v l o v i n a g n d i n t s s 2 6 v i n 2 7 2 9 e n / u v l o v i n a g n d r u v l o 1 r u v l o 2 i n t s s 2 6 v i n 2 7 2 9
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 25 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module the v on uvlo threshold must be set to at least (v out + 3 v) or 6.5 v whichever is higher to insure proper startup and reduce current surges on the host input supply as the voltage rises. if possible, it is recommended to set the uvlo threshold to approximately 80 % to 85% of the minimum expected input voltage. v off should be selected to be at least 500 mv less than v on . use equation 6 and 7 to calculate the values of r uvlo1 and r uvlo2 . r uvlo1 = v on ? v off 2 . 9 ? 10 ? 3 k ( 10 ) r uvlo2 = 1 . 25 v on ? 1 . 25 r uvlo1 + 0 . 9 ? 10 ? 3 k ( 11 ) table 4 lists standard resistor values for r uvlo1 and r uvlo2 for adjusting the v on uvlo threshold for several input voltages. v on threshold r uvlo1 r uvlo2 6.5v 174k? 40.2k? 24.3k? 15.8k? 11.5k? 9.09k? 7.5k? 6.34k? 5.62k? 4.99k? table 4 : standard v on threshold values
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 26 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module step 7 optional: enable / disable the en pin provides electrical on/off control of the device. once the en pin voltage exceeds the threshold voltage, the device starts operation. if the en pin voltage is pulled below the threshold voltage , the regulator stops switching and enters low quiescent current state. figure 7 shows the typical application of the enabl e function. the en pin has an internal pull - up current source, allowing the user to float the en pin for enabling the device. if an application requires controlling the en pin, use an open drain/collector device, or a suitable logic gate to interface with the pin. turning q1 on applies a low voltage to the enable (en) pin and disables the output of the supply shown in figure 9 . if q1 is turned off, the supply executes a soft - start power - up sequence, as shown in figure 8 . a regulated output voltage is produ ced within 5ms. figure 7 . typical enable/disable control figure 8 . en start - up i out = 2a figure 9 . en shut down i out = 2a e n / u v l o v i n a g n d r u v l o 1 r u v l o 2 i n t s s 2 6 v i n 2 7 2 9 e n c o n t r o l q 1 2 m s / d i v v e n 5 v / d i v v s s 1 v / d i v v o u t 2 v / d i v 1 0 0 s / d i v v e n 5 v / d i v v s s 1 v / d i v v o u t 2 v / d i v
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 27 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module step 8 optional: voltage tracking in some applications where a digital ic with 2 or more v cc pins are supplied by the power modules the simultaneous voltage rise on those pins during start up might be required (see figure 11). typical examples are, power supply of most fpgas, dsps, or other microprocessors. in these systems the higher voltage, v o ut1 , usually powers the i/o, and the lower voltage, v out2 , powers the core. this can be realized using the tracking function of the magi3c power module. one module (often the higher output rail) is set up as the master (see figure 10, module 1). the slave module (module 2) has to be connected via the resistive divider r1 tr and r2 tr to the output voltage rail of the primary voltage rail (v out1 ). the slave module output voltage is lower than that of the master. a typical power up sequence would start at t 0 b y setting the en pin to a level above the v en threshold to turn on module 1. after a short delay both output voltages start rising simultaneously. the lower output voltage (v out2 ) reaches its nominal level first at time t 1 . the master module reaches its nominal level (v out1 ) later at t 2 . proper configuration allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails during ramp - up is small (i.e.<0.15v typ). the values for the tracking resistive div ider should be selected such that the effect of the internal 2a current source is minimized. in most cases the ratio of the tracking divider resistors is the same as the ratio of the output voltage setting divider. proper operation in tracking mode dictat es the soft - start time of the slave rail to be shorter than the master rail. therefore place an external soft - start capacitor at the master module1 . figure 10 . voltage tracking configuration en / uvlo ss / trk intss vout en / uvlo ss / trk intss vout r 1 r 2 27 27 28 28 29 29 c ss agnd agnd v on v out 1 v out 2
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 28 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module figure 11. simultaneous voltage tracking waveforms first select r2 tr . a value below 10k is recommended. use equation 8 to calculate the resistor r1 tr . r1 tr = ( v out2 0 . 8 ? 1 ) ? r2 tr ( 12 ) for proper operation the following condition must be assured: v out2 < 0 . 8 ? v out1 ( 13 ) v en 0 t 0 t v on v out enable threshold t 0 v out 1 v out 2 t 1 t 2
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 29 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module step 9 optional: synchronization to an external clock an internal phase locked loop (pll) allows synchronization between 300 khz and 1 mhz, and to easily switch from rt mode to clk mode. to implement the synchronization feature, connect a square wave clock signal to the rt/clk pin with a duty cycle between 20 % to 80 %. the clock signal amplitude must transition lower than 0.8 v and higher than 2.0 v. the start of the switching cycle is synch ronized to the falling edge of rt/clk pin. in applications where both rt mode and clk mode are needed, the device can be configured as shown in figure 12. before the external clock is present, the device works in rt mode where the switching frequency is se t by the r rt resistor. when the external clock is present, the clk mode overrides the rt mode. the first time the clk pin is pulled above the rt/clk high threshold (2.0 v), the device switches from rt mode to clk mode and the rt/clk pin becomes high impeda nce as the pll starts to lock onto the frequency of the external clock. it is not recommended to switch from clk mode back to rt mode because the internal switching frequency drops to 100 khz first before returning to the switching frequency set by the r rt resistor. figure 1 2 . synchronization configuration step 10 optional: power good (pg) the pg pin is an open drain output. once the output voltage is between 94 % and 106 % of the set voltage, the pg pin pull - down is released and the pin floats. the recommended pull - up resistor value is between 10 k and 100 k to a voltage source that is 5.5 v or less. the pg pin is in a defined state once v in is higher than 1.0 v, but with reduced current sinking capability. the pg pin achieves full current sinking capability once the v in pin is above 4.5 v. the pg pin is pulled low when the output voltage is lower than 91 % or higher than 109 % of the nominal set voltage. also, the pg pin is pulled low if the input uvlo or thermal shutdown is asserted, the en pin is pulled low, or the ss/trk pin is below 1.4 v. r t / c l k a g n d 1 k ? r r t s s c h o 4 7 0 p f e x t e r n a l c l o c k 3 0 0 k h z t o 1 m h z 0 6 s 2 9 3 1 pg 10 k? v cc = v in or other supply voltage below 5 . 5 v 35 v cc agnd
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 30 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module light load operation the magi3c power module is a non - synchronous converter. one of its characteristics is, that as the load current on the output is decreased a point is reached where the energy delivered by a single switching pulse is more than the load can absorb. this causes the output voltage to rise slightly. this rise in output voltage is sensed by the feedback loop and the device responds by skipping one or more switching cycles until the output voltages falls back to the set point. at very light loads or no load, many switching cycles are skipped. the observed effect during this pulse skipping mode of operation is an increase in the peak to peak ripple voltage, and a decrease in the ripple frequency. the load current at which pulse skipping begins is a function of the input voltage, the output volt age, and the switching frequency. a plot of the pulse skipping threshold current as a function of input voltage is given in figure 13 for a number of popular output voltage and switching frequency combinations. figure 1 3 . pu lse skipping load threshold 2 7 d o u t p u t c u r r e n t ( m a ) i n p u t v o l t a g e ( v ) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 2 . 5 v / 4 0 0 k h z 3 . 3 v / 4 0 0 k h z 5 . 0 v / 4 0 0 k h z 9 v / 6 0 0 k h z 1 2 v / 8 0 0 k h z 1 5 v / 1 m h z
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 31 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module pcb layout instructions: pc board layout is an important part of dc - dc converter design. poor board layout can disrupt the performance of a dc - dc converter and surrounding circuitry by contributing to emi, ground bounce and resistive voltage drop in the traces. these can send erroneous signals to the dc - dc converter resulting in poor regulation or instability. good layout can be implemented by following five simple design rules. 1: minimize area of switched current loops target is to identify the paths in the system which have discontinuous current flow. they are the most critical ones because they act as an antenna and cause observable high frequency noise (emi). the easiest approach to find the critical paths is to draw the high current loops during both switching cycles and identify the sections which do not overlap . they are the ones where no continuous current flows and high di/dt is observed. loop 1 is the current path during the on - time of the high - side mosfet . loop 2 is the current path during the off - time of the high - side mosfet . based on those considerations, the path of the input capacitor c in is the most critical one to generate high frequency noise on vin. therefore place c in as close as possible to the magi3c power module v in and pgnd pins . this will minimize the high di/dt area and reduce radiated emi. additionally, grounding for both the i nput and output capacitor should consist of a localized top side plane that connects to the pgnd pins . c i n v i n p g n d v o u t p o w e r m o d u l e c o u t l o o p 1 l o o p 2 h i g h d i / d t v i n v o u t v i n v i n f b p g n d v o u t m o d u l e r s e t c o u t a g n d c i n v o u t
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 32 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module the placement of the input capacitors is highlighted in the following picture of the reference board: 2: have a single point ground the gro und connections for the clock setting, soft - start, and enable components should be routed to the a gnd pin of the device. this prevents any switched or load currents from flowing in the analog ground traces. if not properly handle d, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. connect the agnd and pgnd copper area at one point at the ground terminal of the first output capacitor . c i n 1 c i n 2 c i n 3 c o u t 1 c o u t 2 r s e t r r t c s s r u v l o 2 r u v l o 1 v i n v o u t p g n d s w a g n d f b e n / u v l o r t / c l k s s / t r k i n t s s p g c i n 1 c i n 2 c i n 3 c o u t 1 c o u t 2 r s e t r r t c s s r u v l o 2 r u v l o 1 v i n v o u t p g n d s w a g n d f b e n / u v l o r t / c l k s s / t r k i n t s s p g
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 33 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module 3: minimize trace length to high impedance p in s the feedback resistor , r set should be located close to the fb pin. since the fb node is high impedance, maintain the copper area as small as possible. the traces from r set should be routed away from the body of the magi3c power module to minimize noise pickup. place r rt , and c ss as close as possible to their respective pins. 4: make input and output terminal connections as wide as possible this reduces any voltage drops on the input or output of the converter and maximizes efficiency. c i n 1 c i n 2 c i n 3 c o u t 1 c o u t 2 r s e t r r t c s s r u v l o 2 r u v l o 1 v i n v o u t p g n d s w a g n d f b e n / u v l o r t / c l k s s / t r k i n t s s p g c i n 1 c i n 2 c i n 3 c o u t 1 c o u t 2 r s e t r r t c s s r u v l o 2 r u v l o 1 v i n v o u t p g n d s w a g n d f b e n / u v l o r t / c l k s s / t r k i n t s s p g
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 34 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module 5: provi de adequate device heat - sinking place a dedicated agnd copper area beneath the magi3c power module. use an array of heat - sinking vias to connect the agnd pad to the ground plane on the bottom pcb layer. if the pcb has a plurality of copper layers, these thermal vias can also be used to make connection to inner layer heat - spre ading ground planes. it is recommended to use a via array as proposed in the picture above with via diameter of 300 m (hole:100m) thermal vias spaced 400m. ensure enough copper area is used for heat - sinking to keep the junction temperature below 125c. 6: isolate high noise areas place a dedicated agnd copper area beneath the magi3c power module. c i n 1 c i n 2 c i n 3 c o u t 1 c o u t 2 r s e t r r t c s s r u v l o 2 r u v l o 1 v i n v o u t p g n d s w a g n d f b e n / u v l o r t / c l k s s / t r k i n t s s p g
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 35 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module determine power losses and thermal requirements of the board for example: v in = 24 ? , v out = 3 . 3 ? , i out = 1 . 5 ? , t amb ( max ) = 85c and t j ( max ) = 125c t amb(max) is the maximum air temperature surrounding the module. t j(max) is the maximum value of the junction temperature according to the operating conditions limit. the goal of the calculation is to determine the characteristics of the re quired heat sink. in case of a surface mounted module this would be the pcb (number of layers, copper area and thickness). these characteristics are reflected in the value of the thermal resistance case to ambient: ca . the basic formula for calculating the operating junction temperature t j of a semiconductor device is as follows: t j = p ic ? loss ? ja + t amb ic - loss are the total power losses within the module ic and are related to the operating conditions. ja is the thermal resistance junction to ambient and calculated as: ja = jc + ca (15 ) jc is the thermal resistance junction to case. combining equation (14) and (15 ) results in the maximum case - to - ambient thermal resistance: ca ( max ) < t j ? max ? t amb ( max ) p ic ? loss ? jc from section thermal specifications use as typical thermal resistance from junction to case jc = jb = 6 . 8 c/w. use the 2 5c power dissipation curves in the typical performance curves section to estimate the p ic - loss for the application being designed. add 20% losses to take into consideration the ambient temperature of 85c.
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 36 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module from the graph we read a power loss of 1.5 w. adding 20% results in a loss of 1.8w. en tering the values in formula (16 ) results in: ca ( max ) < 125c ? 85c 1 . 8 ? ? 6 . 8c / w = 15 . 42 c / w ja ( max ) = jc + ca ( max ) = 6 . 8c / w + 15 . 42 c / w = 22 . 2 c / w ja < 22 . 2c / w and only natural convection (i.e. no air flow) , the minimum pcb area should be slightly smaller than 60cm 2 . this corresponds to a square board with 7,6 cm x 7,6 cm copper area, 4 layers, and 35m copper thickness. higher copper thickness will further improve the overall thermal performance. note that thermal vias should be placed under the ic package to easily transfer heat from the top layer of the pcb to the inner layers and the bottom layer. 0 6 d p o w e r l o s s [ w ] o u t p u t c u r r e n t [ a ] p o w e r l o s s : v i n = 2 4 v @ t a m b = 2 5 c 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 0 1 2 3 4 5 6 v o u t = 5 . 0 v , f s w = 5 0 0 k h z v o u t = 3 . 3 v , f s w = 4 0 0 k h z v o u t = 2 . 5 v , f s w = 4 0 0 k h z v o u t = 1 2 v , f s w = 8 0 0 k h z v o u t = 1 5 v , f s w = 1 0 0 0 k h z
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 37 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module p rotective features over current protection (ocp) for protection against load faults, the magi3c power module incorporates cycle - by - cycle current limiting. during an overcurrent condition the output current is limited and the output voltage is reduced, as shown in figure 14 . as the output voltage drops more than 8% below the set point, the pg signal is pulled low. if the output voltage drops more than 25% during an overcurrent condition , the module skips switching cycles to reduce power dissipation within the device. when the overcurrent condition is removed, the output voltage returns to the e stablished voltage. the magi3c power module is not designed to endure a sustained short circuit condition. the use of an output fuse, voltage supervisor circuit, or other overcurrent protection circuit is recommended. a recommended overcurrent protection c ircuit is shown in figure 15 . this circuit uses the pg signal as an indication of an overcurrent condition. as pg remains low, the tlc555 timer operates as a low frequency oscillator, driving the en/uvlo pin low for approximately 400ms, halting the power c onversion of the device. after the inhibit interval, the en/uvlo pin is released and the magi3c power module restarts. if the overcurrent condition is removed, the pg signal goes high, resetting the oscillator and power conversion resumes, otherwise the in hibit cycle repeats. figure 14. overcurrent limiting figure 15. over - current protection circuit over temperature protection (otp) the junction temperature of the magi3c power module should not be allowed to exceed its maximum ratings. thermal protection is impl emented by an internal thermal s hutdown circuit which activates at 180c (typ) causing the device to enter a low power standby state. in this state the main mosfet remains off causing v out to fall, and additionally the c ss capacitor is discharged to ground. thermal protection helps prevent catastrophic failures for accidental device overheating. when the junction temperature falls back below 165 the ss pin is released, v out rises smoothly, and functional operation resumes. please note that an operation of the junction above 125c is not recommended. applications requiring maximum output current especially those at high input voltage may require additional derating at elevate d temperatures 2 v / d i v 5 a / d i v 5 v / d i v v p w r g d 1 0 0 s / d i v 2 8 d i o u t v o u t c o n t d i s t l c 5 5 5 o u t r s t g n d t h r s t r i g v d d 1 f 4 7 . 5 k 1 0 0 k 1 0 0 k 4 7 5 k 3 . 3 v / 5 v 3 . 3 v / 5 v t o e n / u v l o p i n 2 7 f r o m p w r g d p i n 3 5 b s s 1 3 8 b s s 1 3 8
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 38 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module a pplications typical application circuit recommended component values specified at t a = 25c v out 12v 5v 3.3v v in 15v to 50v 8v to 50v 7v to 36v r set 140k? 52.3k? 31.6k? r uvlo1 174k? 174k? 174k? r uvlo2 15.4k? 31.6k? 40.2k? r rt 267k? 1.1m? open c in1 min 2.2f; 100v 2.2f; 100v 4.7f; 50v c in2 2.2f; 100v 2.2f; 100v open c out1 min 47f; 16v 47f; 6.3v 47f; 6.3v c out2 47f; 16v 47f; 6.3v 47f; 6.3v c ss 22nf open open c i n 2 e n / u v l o v i n r t / c l k p g n d s s / t r k f b v o u t m o d u l e r s e t c s s c o u t 1 a g n d 2 6 2 7 3 1 2 8 3 6 v i n v o u t s s c h o 2 9 p g 3 5 r u v l o 1 r u v l o 2 r r t c i n 1 c o u t 2
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 39 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module evaluation board schematic bill of material designator description quantity order code manufacturer ic1 magi 3 c power module 1 171021501 wrth elektronik c in1 aluminium electrolythic capacitor 27 f /100v 1 860040874001 wrth elektronik c in2 ,c in3 ceramic chip capacitor 4,7f/100 v x5r 2 c out1 c eramic chip capacitor 100nf/100 v x7r 0805 1 c out2 ,c out3 ceramic chip capacitor 22f/25 v x7r 2 885012109014 wrth elektronik c out4 aluminium polymer electrolythic capacitor 33 f /25v 1 875105545004 wrth elektronik c ss , c sync not mounted c f ( 1 ) filter ceramic chip capacitor 2.2 f/100v 1 l f (2 ) filter inductor 22 h, pd2 1 744774122 wrth elektronik r uvlo1 , r uvlo2 , r sync not mounted r 1 12.4 k 1 r 2 12.4 k 1 led1 led red 1 150080ss75000 wrth elektronik r rt set by jumper open for f sw = 400khz 1.1m for f sw = 500khz 1 549k for f sw = 600khz 1 365k for f sw = 700khz 1 267k for f sw = 800khz 1 215k for f sw = 900khz 1 178k for f sw = 1mhz 1 r set set by jumper 21.5k for v out = 2.5v 1 31.6k for v out = 3.3v 1 52.3k for v out = 5v 1 102k for v out = 9v 1 140k for v out = 12v 1 178k for v out = 15v 1 (1) not mounted on the evaluation board (2) not mounted on the evaluation board . a shorting wire or 0r resistor is put in its place c in 1 en / uvlo vin rt / clk pgnd ss / trk fb vout module r set c ss c out 1 agnd 26 27 31 28 36 v in v out sscho 29 pg 35 r rt c in 2 c out 3 c in 3 c out 2 ic 1 c f l f r 1 r 2 led 1 c out 4 r uvlo 1 r uvlo 2 r sync c sync ext . clock optional input filter
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 40 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module handling recommendations 1. f s older profile 1. only pb - free assembly is recommended according to jedec j - std020. 2. measure the peak reflow temperature of the magi3c power module in the middle of the top view. 3. ensure that the peak reflo w temperature does not exceed 245 c 5c as per jedec j - std020. 4. the reflow time period during peak temperature of 24 5 c 5c must not exceed 3 0 seconds. 5. reflow time above li quidus (217c) must not exceed 9 0 seconds. 6. maximum ramp up is rate 3c per second 7. maximum ramp down rate is 3 c per second 8. reflow time from room (25c) to peak must not exceed 8 minutes as per jedec j - std020. 9. maximum numbers of reflow cycles is three . 10. for minimum risk, solder the module in the last reflow cycle of the pcb production. 11. for soldering process please consider lead material copper (cu) and lead finish tin (sn). 12. for solder paste use a standard sac alloy such as sac 305, type 3 or higher. 13. below profile is valid for convection reflow only 14. other soldering methods (e.g.vapor phase) are not verified and have to be validated by the customer on his own risk t e m p e r a t u r e [ c ] t i m e [ s e c ] 1 5 0 1 8 0 2 1 7 m a x 2 5 0 m a x 1 2 0 s e c m i n 6 0 s e c m a x 9 0 s e c m i n 3 0 s e c m a x 1 0 - 3 0 s e c 2 4 5 c r a m p u p r a t e m a x 3 c / s e c r a m p d o w n r a t e m a x 3 c / s e c m a x 3 s o l d e r c y c l e s ! p r e h e a t l i q u i d u s p e a k
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 41 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module physical dimensions (mm) package type: bqfn - 41 (9 x 11 x 2.8mm)
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 42 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module recommended soldering pad solder past recommendation 150 m
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 43 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module p ackaging reel (mm) 2 0 p
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 44 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module tape (mm) 2 2 p b q f n - 4 1 1 1 , 3 5 9 , 3 5 0 , 1 0 , 1 0 , 0 5 0 , 3 0 0 , 1 3 , 1 0 0 , 0 5 1 , 5 5 0 , 1 0 m a r k i n g m a r k i n g m a r k i n g m a r k i n g m a r k i n g m a r k i n g
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 45 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module d ocument history revision date description comment 1.0 may 2016 release of f inal version c autions and warnings the following conditions apply to all goods within the product series of magi3c of wrth elektronik eisos gmbh & co. kg: general: all recommendations according to the general technical specifications of the data - sheet have to be complied with. the usage and operation of the product within ambient conditions which probably alloy or harm the component surface has to be avoided. the responsibility for the applicability of customer specific products and use in a particular customer design is always within the authority of the customer. all technical specifications for standard products do also apply for customer specific products. residual w ashing varnish agent that is used during the production to clean the application might change the characteristics of the body, pins or termination. the washing varnish agent could have a negative effect on the long te r m function of the product. direct mechanical impact to the product shall be prevented as the material of the body, pins or termination could flake or in th e worst case it could break. as these devices are sensitive to electrostatic discharge customer shall follow proper ic handling procedures. customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety - related requirements concerning its products, and any use of wrth elektronik eisos gmbh & co. kg components in its applications, notwithstanding any applications - related information or support that may be provided by wrth elektronik eisos gmbh & co. kg. customer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions. customer will fully indemnify wrth elektronik eisos and its representatives against any damages arising out of the use of any wrth elektronik eisos gmbh & co. kg components in safety - critical applications. product specific: follow all instructions mentioned in the datasheet, especially: ? the solder profile has to comply with the technical reflow or wave soldering specification, otherwise this will void the warranty. ? all products are supposed to be used before the end of the period of 12 months based on the product date - code . ? violation of the technical product specifications such as exceeding the absolute maximum ratings will void the warranty. ? it is also recommended to return the body to the original moisture proof b ag and reseal the moisture proof bag again. ? esd prevention methods need to be followed for manual handling and processing by machinery.
we - online.com ? may 2016 wrth elektronik eisos gmbh & co. kg - data sheet - rev 1.0 46 / 46 wpmdu1251501 / 17102150 1 magi3c power module v drm - variable step down regulator module important notes the following conditions apply to all goods within the product range of wrth elektronik eisos gmbh & co. kg: 1. general customer responsibility some goods within the product range of wrth elektronik eisos gmbh & co. kg contain statements regarding general suitability for certain application areas. these statements about sui tability are based on our knowledge and experience of typical requirements concerning the areas, serve as general guidance and cannot be estimated as binding statements about the suitability for a customer application. the responsibility for the applicabil ity and use in a particular customer design is always solely within the authority of the customer. due to this fact it is up to the customer to evaluate, where appropriate to investigate and decide whether the device with the specific product characteristi cs described in the product specification is valid and suitable for the respective customer application or not. accordingly, the customer is cautioned to verify that the datasheet is current before placing orders. 2. customer responsibility related to sp ecific, in particular safety - relevant applications it has to be clearly pointed out that the possibility of a malfunction of electronic components or failure before the end of the usual lifetime cannot be completely eliminated in the current state of the a rt, even if the products are operated within the range of the specifications. in certain customer applications requiring a very high level of safety and especially in custome r applications in which the malfunction or failure of an electronic component coul d endanger human life or health it must be ensured by most advanced technological aid of suitable design of the customer application that no injury or damage is caused to third parties in the event of malfunction or failure of an electronic component. 3. best care and attention any product - specific notes, warnings and cautions must be strictly observed. 4. customer support for product specifications some products within the product range may contain substances which are subject to restrictions in certain jurisdictions in order to serve specific technical requirements. necessary information is available on request. in this case the field sales engineer or the internal sales person in charge should be contacted who will be happy to support in this matter. 5 . product r&d due to constant product improvement product specifications may change from time to time. as a standard reporting procedure of the product change notification (pcn) according to the jedec - standard we inform about minor and major changes. in ca se of further queries regarding the pcn, the field sales engineer or the internal sales person in charge should be contacted. the basic responsibility of the customer as per section 1 and 2 remains unaffected. 6. product life cycle due to technical progress and economical evaluation we also reserve the right to discontinue production and delivery of products. as a standard reporting procedure of the product termination notification (ptn) according to the jedec - standard we will inform at an early stag e about inevitable product discontinuance. according to this we cannot guarantee that all products within our product range will always be available. therefore it needs to be verified with the field sales engineer or the internal sales person in charge abo ut the current product availability expectancy before or when the product for application design - in disposal is considered. the approach named above does not apply in the case of individual agreements deviating from the foregoing for customer - specific prod ucts. 7. property rights all the rights for contractual products produced by wrth elektronik eisos gmbh & co. kg on the basis of ideas, development contracts as well as models or templates that are subject to copyright, patent or commercial protection su pplied to the customer will remain with wrth elektronik eisos gmbh & co. kg. wrth elektronik eisos gmbh & co. kg does not warrant or represent that any license, either expressed or implied, is granted under any patent right, copyright, mask work right, o r other intellectual property right relating to any combination, application, or process in which wrth elektronik eisos gmbh & co. kg components or services are used. 8. general terms and conditions unless otherwise agreed in individual contracts, all or ders are subject to the current version of the genera l terms and conditions of wrth elektronik eisos group, last version available at www.we - online.com .

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